Skip navigation

Tag Archives: VHDL

A long time ago I picked up an old LCD module (this one, if its still there). Now the trouble with this module is that it does not have a built in controller. It’s more like a TV or monitor in that it needs to constantly be fed a signal containing the image data to display. Now a standard micro controller might have trouble doing this on its own, it would either require a bit of external circuitry, or have to dedicate the majority of it’s processing time to updating the display. This is a surplus part, and the datasheet provided is poorly xeroxed and lacking specific implementation details. However it is a nice monochrome display at 640×480 and well worth the price of $5.50, if you can get it to work. Luckily for me, I found one other person on the whole internet who managed to get this same display working, and remnants of his work for the MIT Model Railroad club were found here, http://www.nyx.net/~jpurbric/lcd/. Now he managed to implement this using a PIC micro, some discrete logic and some external memories. My plan is to first attempt to drive this from my Papilio board. I had a good start since this other project made really nice timing diagram to follow for the display.

First in implementing the VHDL, I defined as many constant values as I could think up. Using the timing diagram and the datasheet, I setup some time period and count constants.

--Timing Constants 
--Time constant integers in nanoseconds
constant CLK_PERIOD : integer := 31; -- approximate/rounded off
constant XSCL_PERIOD : integer := 166 ;

--FRAME CONSTANTS 	
constant WIDTH : integer := 640;
constant HEIGHT : integer := 480;
constant XPULSES : integer := WIDTH / 4;
constant YPULSES : integer := 242;

The timings I defined at the minimums defined in the datasheet. The nice part about utilizing constants like this, is that I can adjust these later and the whole design should adjust. The CLK_PERIOD constant is the main clock period, so it will be used to keep track of elapsed time. The XSCL_PERIOD is the minimum period of the XSCL pulse or “X Shift Clock”. Looking at the timing diagram it seems that the data is read in on the negative edge of this signal. At first I thought of several other timing constants, but as I worked out the design, they didn’t prove to be necessary. The other constants are pretty obvious, the HEIGHT and WIDTH of the screen in pixels, and the number of YPULSES and XPULSES to be sent in each frame of the signal. If you notice these numbers don’t match up to the size of the display. This display is organized as two screens, an upper and lower half. It’s also 1 bit per pixel. So, of the 8 bit data bus, 4 bits go to the top and 4 go to the bottom. So it only needs to write 160 times for each line to get 640 pixels and it will write 242 lines. Yeah, there are 2 extra lines in the signal but the don’t make it to the display. And now for a couple signals to get started with.

 --Timing signals
signal XSCL_TIME : integer range 0 to (XSCL_PERIOD + CLK_PERIOD) := 0;

--count signals 
signal XSCL_CNT : integer range 0 to 160 := 0;
signal YSCL_CNT : integer range 0 to 242 := 0;

The first is my main time delay count. XSCL_TIME will just add on the clock period each time through the main process to make sure we don’t violate our minimum time for the signal. Its defined as a range from zero to XSCL_PERIOD + CLK_PERIOD because I wanted to be sure that whatever size value it ends up being has enough room exceed the XSCL_PERIOD by one clock cycles worth. The XSCL_CNT and YSCL_CNT are regular increment counters to keep track of where we are in the signal and be the main drivers of the state machine.

signal STARTED : STD_LOGIC := '0';

The STARTED signal is just a flag that’s used to have the signal go through as start up process. After the start up, STARTED is set to 1 and stays there.

--Output Signals 
signal LP_YSCL : STD_LOGIC := '0';
signal XSCL : STD_LOGIC := '0';
signal UD : STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal LD : STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal DIN : STD_LOGIC := '0';

These are the various output signals, three timing signals and the data signals. For now we will just be sending test pattern on the data. Now for the main process. I think its well commented so I won’t give a line by line explaination. It’s basically a simple state machine, using the current state of the output signals, the XSCL_CNT/YSCL_CNT, and XSCL_TIME signals to track where it is in the process. It follows right along with the timing diagram. Remember that in the process, signals are not updated until after the process.

	--Process Definition
	main: process(clk)
   begin
		-- triggers action on rising edge of clock signal
     if rising_edge(clk) then
	    --increment counter, using time type
		 XSCL_TIME <= XSCL_TIME + CLK_PERIOD;
		 
		 
		 if STARTED='0' then
		   --initial state
			--first part of timing diagram, on LP pulse, and a up/down on XSCL
			if LP_YSCL = '0' then 
				--set signals
				LP_YSCL <= '1';
				XSCL <= '1';
				--reset times
				XSCL_TIME <=0;
			elsif LP_YSCL = '1' and 
						XSCL = '1' AND
						XSCL_TIME > (XSCL_PERIOD/2) then 
				--set signal
				XSCL <= '0';
			elsif LP_YSCL = '1' AND
						XSCL = '0' AND 
						XSCL_TIME > XSCL_PERIOD THEN 
				--clear started flag
				STARTED <= '1';
				--reset timer
				XSCL_TIME <= 0;
			end if;
		else
			--after started
			if LP_YSCL = '0' and
				XSCL = '0' and 
				XSCL_CNT = 0 THEN
				--occurs at the end of a row, timing specs say LP_YSCL must go to zero before XSCL goes high
				--Raise XSCL to HI			
				XSCL <= '1';
				--reset pulse timer 
				XSCL_TIME <= 0;
				
				--update X count 
				XSCL_CNT <= XSCL_CNT + 1;
			elsif LP_YSCL = '1' and 
			--first step, LP is H, XSCL is L, XSCL_CNT is 0
				XSCL = '0' AND
				XSCL_CNT = 0 THEN 
				
				--drop LP, Raise XSCL, load data
				LP_YSCL <= '0';
				XSCL <= '1';
				
				--temp data 
				UD <= "0101";
				LD <= "0101";
				
				--reset timer
				XSCL_TIME <= 0;
				
				--if first row, raise frame pulse
				if YSCL_CNT = 0 then 
					DIN <= '0';
				end if;
			elsif XSCL = '1' AND 
					XSCL_TIME > (XSCL_PERIOD/2) THEN
				--drop xscl to L
				XSCL <= '0';
				
			elsif XSCL = '0' AND 
					XSCL_TIME > XSCL_PERIOD THEN
								
				
				--load new data
				--TODO
				
				--IF at last pulse raise LP to hi
				if XSCL_CNT = XPULSES - 2 then -- use pulses-2 to compensate for cnt not updated yet and zero based index.
					--last X pulse, raise LP
					LP_YSCL <= '1'; 
					--update X count 
					XSCL_CNT <= XSCL_CNT + 1;
					
					--Raise XSCL to HI			
					XSCL <= '1';
					--reset pulse timer 
					XSCL_TIME <= 0;
					
				elsif XSCL_CNT = XPULSES - 1 THEN 
				   --new line, drop LP
					LP_YSCL <= '0';
					--reset XSCL_CNT
					XSCL_CNT <= 0;
					
					if YSCL_CNT = YPULSES - 1 then 
						-- this was the last pulse, go back to zero
						YSCL_CNT <= 0;
					else						
						--increment Y count
						YSCL_CNT <= YSCL_CNT + 1;
					end if;
					
				else					
					--Raise XSCL to HI			
					XSCL <= '1';
					--reset pulse timer 
					XSCL_TIME <= 0;
					--update X count 
					XSCL_CNT <= XSCL_CNT + 1;
				end if;
				
			end if;	
			
			--if on first line, first x, raise frame pulse
			if LP_YSCL = '0' AND 
				XSCL = '1' AND
				XSCL_CNT = 0 and 
				YSCL_CNT = 0 then 
				--raise frame pulse
				DIN <= '1';
			elsif LP_YSCL = '0' AND 
					XSCL = '1' AND 
					XSCL_CNT = 0 AND 
					YSCL_CNT = 1 then 
				--shut down frame pulse 
				DIN <= '0';
			end if;
				
		 end if; --started
		 		
     end if; --clk	 
 	  
   end process;

And the most important part, mapping the signals to the output pin.

	A(0) <= LP_YSCL;
	A(1) <= XSCL;
	A(5 downto 2) <= UD;
	A(9 downto 6) <= LD;
	A(10) <= DIN;

I currently don’t have it setup to connect the display to the FPGA board just yet. I need to wire that up with a 3.3 to 5 logic conversion, since the Spartan3 is a 3.3V part. And looking at the datasheet the minimum “1” voltage is .8*VDD and the minimum VDD is 4.75V. Assuming a 5V supply, I need at least 4V to drive these signals. However, I really should verify the output of this before I go through the trouble of hooking it up anyways. Thankfully, the Xilinx tools come with a simulator that can be used to verify your design.

SimulateDesign

If you click on your source file in the design explore on the left, select Simulation up top, and the right click on ‘Simulate Behavioral Model’ and select ‘Run’, you should be see the ISim window open up. For me, the first thing I had to do was setup the clock. Oddly, it runs the simulation first with the clock just set as ‘Undefined’. Under the simulation menu, click ‘Restart’ to clear out the current simulation. Right click on the ‘clk’ signal, and select ‘Force Clock’.

ForceClockRightClick

Then you enter the parameters for your clock signal. I really wasn’t sure of the meaning of ‘Leading Edge Value’ and ‘Trailing Edge Value’ so I entered 1 and 0 respectively as they are required fields. Then I just set the clock period of 31.25ns.

DefineClock

Once you’ve done that, can run that for the amount of time you want to see. These commands should be on the toolbar at the top of the window.

RunForTime

Each time you click on the ‘Run for Time Specified’ button, it will add to the simulation, so you can verify the signal a few blocks at a time.

LCDSimulation

Looks good so far. Hopefully soon I can get it wired up and see if it actually works.

I was just recently aquired an 8×8 RGB LED matrix, similar to this one. I though it would be good practice to wire up the Papilio board to it an write up some VHDL to drive the display.

2013-10-02 23.55.48

As you can see on the datasheet, this is a common anode display, meaning that the positive voltage will be supplied to the 8 common terminals to operate. The pinout is pretty simple, 1 through 8 are the blue cathodes, which I connected to pins B0-B7 on the board. 9 through 16 are the green cathodes, which are connected to pins A8-A15 board. Pins 21 through 28, are the red cathodes and are connected to the boards B15-B8 pins. Pins 17,18,19,20,29,30,31,32 are the anodes and are connected to pins A0-A7 on the board. I included some small 360 ohm resistors on the anodes, just to limit the current. However the LEDs are not very bright as such. Its much brighter, and I *think* it’s safe to drive the outputs directly from the pins. Otherwise some simple buffer drivers I’m sure would produce a much brighter result.

As for the code, I started off with some of the same stuff from the last LED matrix. The PWM drive is the same, but I changed the counter from 8 bit to 4 bit. It simply counts up, and as long as the counter is less than the set value, the output bit is on.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity PWM is
    Port ( Value_In : in  integer range 0 to 15 ; --input for pwm value
           Bit_Out : out  STD_LOGIC;					--pwm output
			  clk : in STD_LOGIC);							--system clock
end PWM;

architecture Behavioral of PWM is

begin

	pwm: process(clk)
		variable count: integer range 0 to 15 := 0; --variable, internal to process, 8 bit counter
	begin
		if rising_edge(clk) then 
			--increment count variable (note variable uses := not <=
			count := count + 1;
			
			if count < Value_In then 
			   --while the counter is less than value, set bit
				--this ensures duty cycle is proportional to value
				Bit_Out <= '1';
			else
				--off during other half of cycle, while counter is greater than value
				Bit_Out <= '0';
			end if;		
				
		end if;
	
	end process;
	


end Behavioral;

For the main code, I decided to just have it display all one color, where the RGB values are cycled through at different rates. I also tried to pull out as much as I could from the main process block, to avoid some of the confusion of values being set after the process completes, which caused actions to be one step behind where I thought they would be. The way I understand it, statements in the architecture block are “wired up” so that changes propagate almost instantly. I added three processes to handle the cycling of the RGB values. The signal ‘counter’ just serves as a delay to time the scanning process. The signal ‘row’ is a 24 bit mask for the cathode pins, where the 0 indicates the pin that is active. The signal ‘col’ is an 8 bit mask for the anode pins, where 1 indicates the active pin. The signal ‘rgb’ is a 3 bit flag which is rotated to keep track of which value, red, green, or blue, should be applied to the currently active cathode pin. ‘col’ is rotated left whenever ‘counter’ rolls back to zero, ‘row’ and ‘rgb’ are rotated left when after ‘col’ is rotated back to its original value. A WITH … SELECT syntax is used to map the different color values into ‘value’ depending on the value of ‘rgb’. ‘value’ is mapped into the PW generator, and ‘pwm_bit’ is mapped as its output. A WHEN … ELSE style assignment is used to enable or disable the ‘col’ flags on the output, which is what ties the PWM drive to the output.


--Standard includes
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Entity definiton
entity First is
    Port ( A : out  STD_LOGIC_VECTOR (15 downto 0); -- maps to pins 0 to 16 of port A
				B : out STD_LOGIC_VECTOR (15 downto 0); --
			  clk : in STD_LOGIC); --clock signal
end First;

--architecture definition
architecture Behavioral of First is

--component definition for the PWM
component PWM is
    Port ( Value_In : in  integer range 0 to 15 ;
           Bit_Out : out  STD_LOGIC;
			  clk : in STD_LOGIC);
end component;
			  
 --Interial signals
 --counter to control state and delay
 signal counter : STD_LOGIC_VECTOR(8 downto 0) := (others => '0'); 
 --signal for LED "rows", anodes. 0 provides ground for selected row
 signal row : STD_LOGIC_VECTOR(23 downto 0) := "111111111111111111111110";				
 --signal for LED "columns", common cathodes. 1 provides + volts for selected column.
 signal col : STD_LOGIC_VECTOR(7 downto 0) := "00000001";				--signal for LED columns
 
 --rgb flag, for selecting R,G,B values to send to selected output
 signal rgb : STD_LOGIC_VECTOR(2 downto 0) := "001";

 --rolling color values																	
 signal red_value : integer range 0 to 15 := 0;		 
 signal green_value : integer range 0 to 15 := 0;					
 signal blue_value : integer range 0 to 15 := 0;					
 --used to retrieve value from array, mapped to PWM input
 signal value : integer range 0 to 15 := 0;	
 
 --counters for timing color changes
 signal red_counter : STD_LOGIC_VECTOR(20 downto 0) := (others => '0');
 signal green_counter : STD_LOGIC_VECTOR(19 downto 0) := (others => '0');
 signal blue_counter : STD_LOGIC_VECTOR(18 downto 0) := (others => '0');
	
 --signal to be mapped to PWM output	
 signal pwm_bit : STD_LOGIC;												

begin 

	--port map for linking to the PWM
	PW1 : PWM port map(Value_In => value, 
							 Bit_out => pwm_bit,
							 clk => clk);
							 

	--route row masks to outputs
	A(15 downto 8) <=  row(22) & row(19) & row(16) & row(13) & row(10) & row(7) & row(4) & row(1); -- green
	B(15 downto 8) <= row(21) & row(18) & row(15) & row(12) & row(9) & row(6) & row(3) & row(0); -- red
	B(7 downto 0) <= row(23) & row(20) & row(17) & row(14) & row(11) & row(8) & row(5) & row(2); -- blue
	
	--route column masks to outputs, only if PWM bit is on
	A(7 downto 0) <= col WHEN pwm_bit = '1' 
								ELSE "00000000";
	
	--route proper RGB value to PWM generator
	WITH rgb SELECT
		value <= red_value WHEN "001",
					green_value WHEN "010",
					blue_value WHEN "100",
				   0 WHEN OTHERS;
					
					
	--Process Definition
	scan_matrix: process(clk)
   begin
		-- triggers action on rising edge of clock signal
     if rising_edge(clk) then
	    --increment counter
       counter <= counter+1;
		 --clock period is 31.25ns, counter is 9 bits, should scan whole matrix in < 1ms
			--trigger each time counter rolls over back to zero 
			if counter = 0 then 
				-- Left Rotate col
				col <= col(6 downto 0) & col(7);

				-- Trigger when last column becomes active
				if col = "10000000" then
					-- Left rotate row
					row <= row(22 downto 0) & row(23);
					-- increment row count
					rgb <= rgb(1 downto 0) & rgb(2);

				end if;
				
			end if;
					
     end if; 	  	  
   end process;
						
		
	--Process Definition
	red: process(clk)
   begin
		-- triggers action on rising edge of clock signal
     if rising_edge(clk) then
			red_counter <= red_counter + 1;
			if red_counter = 0 then 
				red_value <= red_value + 1;
			end if;
	  end if;
	end process;
	  
	  	--Process Definition
	blue: process(clk)
   begin
		-- triggers action on rising edge of clock signal
     if rising_edge(clk) then
			blue_counter <= blue_counter + 1;
			if blue_counter = 0 then 
				blue_value <= blue_value + 1;
			end if;
	  end if;
	end process;
	
		--Process Definition
	green: process(clk)
   begin
		-- triggers action on rising edge of clock signal
     if rising_edge(clk) then
			green_counter <= green_counter + 1;
			if green_counter = 0 then 
				green_value <= green_value + 1;
			end if;
	  end if;
	end process;
	
	
		
	
end Behavioral;

Continuing with my learning experiments with the LED Matrix attached to the Papilio dev board, today I am adding PWM output to generate different light intensities. If your not familiar with PWM (pulse width modulation), it’s just a simple digital to analog conversion technique where the pin is switched on and off very fast, so the output effectively becomes an analog average between the time it’s on and the time is off. This is done by changing the duty cycle, which is the ratio to on time versus off time. In our VHDL project, this is a good opportunity to explore adding a new file to the project, a new entity, and interfacing multiple entities together. I added the new file for the PWM entity through the ISE Project Navigator, and followed the wizard, basically just giving the name of the file, entity, and the ports. The ports for this entity are pretty simple, we just need a value in to set the output of the PWM, the output bit, and the system clock in. I added a single process to the architecture, and this time decided to use a variable for internal counting instead of a signal. See this question about signals versus variables. Also being a little different from the code of parts 1 and 2, I am using the integer type, with the range specification. The operation of the PWM is really simple, each rising clock edge, the count variable is incremented. When the count is greater than the set value, the output is turned on, else its turned off. No other logic is needed since the count will keep rolling over back to zero. The higher the set value, the longer the bit stays on, and the higher the output. Just to note, with our clock period set at 31.25nS, and our count variable declared as 0 to 255, our wave will be exactly 256 clock cycles long, or 8uS. That comes out to be a 125KHz PWM frequency. Here’s the code for that part. I deleted out some of the automatic comments the wizard inserted in the file.



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity PWM is
    Port ( Value_In : in  integer range 0 to 255 ; --input for pwm value
           Bit_Out : out  STD_LOGIC;					--pwm output
			  clk : in STD_LOGIC);							--system clock
end PWM;

architecture Behavioral of PWM is

begin

	pwm: process(clk)
		variable count: integer range 0 to 255 := 0; --variable, internal to process, 8 bit counter
	begin
		if rising_edge(clk) then
			--increment count variable (note variable uses := not <=
			count := count + 1;

			if count < Value_In then
			   --while the counter is less than value, set bit
				--this ensures duty cycle is proportional to value
				Bit_Out <= '1';
			else
				--off during other half of cycle, while counter is greater than value
				Bit_Out <= '0';
			end if;

		end if;

	end process;



end Behavioral;

That seems like it will work. Now the trouble I had after this was trying to figure out how to tie the main entity in with this one so I could use it. I changed quite a bit of other stuff in the code to, since we now have to support multiple values for each LED, not just single bit on and off. I changed the display array to be a 2 dimensional array of 8 bit integers. The declaration and instantiation looked like this.


 type display_t is array(7 downto 0, 7 downto 0) of integer range 0 to 255; --array type for new image data, a 2d array of integers
 signal display : display_t := ((1, 1, 1, 1, 1, 1, 1, 1 ),
											(3, 3, 3, 3, 3, 3, 3, 3) ,
											(7, 7, 7, 7, 7, 7, 7, 7) ,
											(15,15,15,15,15,15,15,15) ,
											(31,31,31,31,31,31,31,31) ,
											(63,63,63,63,63,63,63,63) ,
											(127,127,127,127,127,127,127,127) ,
											(255,255,255,255,255,255,255,255 ));

With the 2D array, i also had to set a row_count and col_count to keep track of the position in the array. I also learned that I can define those as ranged integers, so they can be used to index the array directly without conversion. As for the col output, I added an if on the PWM output that would use the col mask if it was true or “00000000” if false. That statement was triggering on the same clock as the PWM so the output will be kept up to the PWM output. Our counter in this process is 9 bits, so each pixel should be getting about 2 PWM waves per scan.

Now to attach the PWM together with the main process here, I learned about the ‘port map’ and ‘component’ structures, component defined under the architecture and port map defined after the architecture’s begin statement. The component I believe acts like a port definition for the referenced entity, and the port map links the signals together.

--component definition for the PWM
component PWM is
    Port ( Value_In : in  integer range 0 to 255 ;
           Bit_Out : out  STD_LOGIC;
			  clk : in STD_LOGIC);
end component;

	--port map for linking to the PWM
	PW1 : PWM port map(Value_In => col_value,
							 Bit_out => pwm_bit,
							 clk => clk);

Looking at the port map, the signal col_value is mapped to PWM’s Value_In, so when we read the pixel value from the array into col_value, it is transferred to the input of the PWM. Likewise, pwm_bit will always be set to the value of the PWM’s Bit_out.

Here is the complete code.


--Standard includes
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Entity definiton
entity First is
    Port ( A : out  STD_LOGIC_VECTOR (16 downto 0); -- maps to pins 0 to 16 of port A
			  clk : in STD_LOGIC); --clock signal
end First;

--architecture definition
architecture Behavioral of First is

--component definition for the PWM
component PWM is
    Port ( Value_In : in  integer range 0 to 255 ;
           Bit_Out : out  STD_LOGIC;
			  clk : in STD_LOGIC);
end component;

 --Interial signals
 signal counter : STD_LOGIC_VECTOR(8 downto 0) := (others => '0'); --counter to control state and delay
 signal row : STD_LOGIC_VECTOR(7 downto 0) := "11111110";				--signal for LED rows
 signal col : STD_LOGIC_VECTOR(7 downto 0) := "00000001";				--signal for LED columns
 type display_t is array(7 downto 0, 7 downto 0) of integer range 0 to 255; --array type for new image data, a 2d array of integers
 signal display : display_t := ((1, 1, 1, 1, 1, 1, 1, 1 ),
											(3, 3, 3, 3, 3, 3, 3, 3) ,
											(7, 7, 7, 7, 7, 7, 7, 7) ,
											(15,15,15,15,15,15,15,15) ,
											(31,31,31,31,31,31,31,31) ,
											(63,63,63,63,63,63,63,63) ,
											(127,127,127,127,127,127,127,127) ,
											(255,255,255,255,255,255,255,255 ));

 signal col_value : integer range 0 to 255 := 0;					--used to retrieve value from array, mapped to PWM input
 signal row_count : integer range 0 to 7 := 1;						--pointer for array
 signal col_count : integer range 0 to 7 := 1;						--pointer for array
 signal pwm_bit : STD_LOGIC;												--signal to be mapped to PWM output

begin

	--port map for linking to the PWM
	PW1 : PWM port map(Value_In => col_value,
							 Bit_out => pwm_bit,
							 clk => clk);

	--Process Definition
	count: process(clk)
   begin
		-- triggers action on rising edge of clock signal
     if rising_edge(clk) then
	    --increment counter
       counter <= counter+1;
		 --clock period is 31.25ns, counter is 9 bits, should scan whole matrix in < 1ms
			--trigger each time counter rolls over back to zero
			if counter = 0 then
				-- Left Rotate col
				col <= col(6 downto 0) & col(7);
				col_count <= col_count + 1;
				-- Trigger when last column becomes active
				if col = "10000000" then
					-- Left rotate row
					row <= row(6 downto 0) & row(7);
					-- increment row count
					row_count <= row_count + 1;
					-- get column mask from current position in array
					col_value <=  display(row_count, col_count);

				end if;
			end if;
			--copy signals to outputs
			A(7 downto 0) <= row;
			--combine column with mask to only display selected pixels
			if pwm_bit = '1' then
				A(15 downto 8) <= (col);
			else
				A(15 downto 8) <= "00000000";
			end if;

     end if;
   end process;




end Behavioral;


And of course, the working example.